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18-bit, 250 ksps, differential programmable input pulsar ? adc ad7631 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2011 analog devices, inc. all rights reserved. features multiple pins/software-programmable input ranges +5 v (10 v p-p), +10 v (20 v p-p), 5 v (20 v p-p), 10 v (40 v p-p) pins or serial spi-compatible input ranges/mode selection throughput: 250 ksps inl: 1.5 lsb typical, 2.5 lsb maximum (9.5 ppm of fsr) 18-bit resolution with no missing codes dynamic range: 102.5 db snr: 101 db @ 2 khz thd: ?112 db @ 2 khz i cmos? process technology 5 v internal reference: typical drift 3 ppm/c; temp output no pipeline delay (sar architecture) parallel (18-/16-/8-bit bus) and serial 5 v/3.3 v interface spi-/qspi?-/microwire?-/dsp-compatible power dissipation 73 mw @ 250 ksps 10 mw @ 1 ksps pb-free, 48-lead lqfp and 48-lead lfcsp (7 mm 7 mm) applications process controls high speed data acquisition digital signal processing spectrum analysis ate general description the ad7631 is an 18-bit, charge redistribution, successive approximation register (sar), architecture analog-to-digital converter (adc) fabricated on analog devices, inc.s i cmos high voltage process. the device is configured through hardware or via a dedicated write-only serial configuration port for input range and operating mode. the ad7631 contains a high speed 18-bit sampling adc, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. a falling edge on cnvst samples the fully differential analog inputs on in+ and in?. the ad7631 features four different analog input ranges. power is scaled linearly with throughput. operation is specified from ?40c to +85c. functional block diagram 18 control logic and calibration circuitry clock ad7631 dgnd dvdd avdd agnd ref refgnd in+ pd reset cnvst pdbuf refbufin pdref ref temp d[17:0] busy rd cs d0/ob/2c ognd ovdd d2/a1 d1/a0 ref amp serial data port parallel interface switched cap dac v c c v ee bipolar ten serial configuration port in? mode0 mode1 06588-001 figure 1. table 1. 48-lead pulsar selection input type res (bits) 100 to 250 (ksps) 500 to 570 (ksps) 570 to 1000 (ksps) >1000 (ksps) bipolar 14 ad7951 differential bipolar 14 ad7952 unipolar 16 ad7651 ad7650 ad7653 ad7660 ad7652 ad7667 ad7661 ad7664 ad7666 bipolar 16 ad7610 ad7665 ad7612 ad7663 ad7671 differential 16 ad7675 ad7676 ad7677 ad7621 unipolar ad7622 ad7623 simultaneous/ 16 ad7654 multichannel unipolar ad7655 differential 18 ad7678 ad7679 ad7674 ad7641 unipolar ad7643 differential bipolar 18 ad7631 ad7634
ad7631 rev. a | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ........................................... 12 terminology .................................................................................... 16 theory of operation ...................................................................... 17 overview...................................................................................... 17 converter operation.................................................................. 17 transfer functions...................................................................... 18 typical connecti on diagram ................................................... 18 analog inputs.............................................................................. 19 driver amplifier choice ........................................................... 20 voltage reference input/output .............................................. 21 power supplies ............................................................................ 22 conversion control ................................................................... 23 interfaces.......................................................................................... 24 digital interface.......................................................................... 24 parallel interface......................................................................... 24 serial interface ............................................................................ 25 master serial interface............................................................... 25 slave serial interface .................................................................. 26 hardware configuration ........................................................... 29 software configuration ............................................................. 29 microprocessor interfacing....................................................... 30 application information................................................................ 31 layout guidelines....................................................................... 31 evaluating performance ............................................................ 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 3/11rev. 0 to rev. a changes to resolution parameter, table 2 .................................... 3 changes to figure 4 and table 6..................................................... 8 added exposed pad notation to outline dimensions ............. 32 2/07revision 0: initial version
ad7631 rev. a | page 3 of 32 specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 2. parameter conditions/comments min typ max unit resolution 18 bits analog inputs differential voltage range, v in (v in+ ) ? (v in? ) 0 v to 5 v v in = 10 v p-p ?v ref +v ref v 0 v to 10 v v in = 20 v p-p ?2 v ref +2 v ref v 5 v v in = 20 v p-p ?2 v ref +2 v ref v 10 v v in = 40 v p-p ?4 v ref +4 v ref v operating voltage range v in+ , v in? to agnd 0 v to 5 v ?0.1 +5.1 v 0 v to 10 v ?0.1 +10.1 v 5 v ?5.1 +5.1 v 10 v ?10.1 +10.1 v common-mode voltage range v in+ , v in? 5 v v ref /2 ? 0.1 v ref /2 v ref /2 + 0.1 v 10 v v ref ? 0.2 v ref v ref + 0.2 v bipolar ranges ?0.1 0 +0.1 v analog input cmrr f in = 100 khz 75 db input current 250 ksps throughput 80 1 a input impedance see analog inputs section throughput speed complete cycle 4.0 s throughput rate 250 ksps dc accuracy integral linearity error 2 250 ksps throughput ?2.5 1.5 +2.5 lsb 3 no missing codes 18 bits differential linearity error 2 ?1 +2.5 lsb transition noise 0.75 lsb unipolar zero error ?0.06 +0.06 %fs bipolar zero error ?0.03 +0.03 %fs zero-error temperature drift 0.5 ppm/c bipolar full-scale error ?0.09 +0.09 %fs unipolar full-scale error ?0.07 +0.07 %fs full-scale error temperature drift 0.5 ppm/c power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy dynamic range v in = 0 to 5 v, f in = 2 khz, ?60 db 100 101.8 db 4 v in = all other input ranges, f in = 2 khz, ?60 db 100 102.5 db signal-to-noise ratio v in = 0 to 5 v, f in = 2 khz 99.5 100.5 db v in = all other input ranges, f in = 2 khz 100 101 db signal-to-(noise + distortion), sinad f in = 2 khz 100 db total harmonic distortion f in = 2 khz 112 db spurious-free dynamic range f in = 2 khz 113 db ?3 db input bandwidth v in = 0 v to 5 v 45 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 500 ns
ad7631 rev. a | page 4 of 32 parameter conditions/comments min typ max unit internal reference pdref = pdbuf = low output voltage ref @ 25c 4.965 5.000 5.035 v temperature drift C40c to +85c 3 ppm/c line regulation avdd = 5 v 5% 15 ppm/v long-term drift 1000 hours 50 ppm turn-on settling time c ref = 22 f 10 ms reference buffer pdref = high refbufin input voltage range 2.4 2.5 2.6 v external reference pdref = pdbuf = high voltage range ref 4.75 5 avdd + 0.1 v current drain 250 ksps throughput 250 a temperature pin voltage output @ 25c 311 mv temperature sensitivity 1 mv/c output resistance 4.33 k digital inputs logic levels v il ?0.3 +0.6 v v ih 2.1 ovdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format parallel or serial 18-bit pipeline delay 5 v ol i sink = 500 a 0.4 v v oh i source = ?500 a ovdd ? 0.6 v power supplies specified performance avdd 4.75 6 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v vcc 7 15 15.75 v vee ?15.75 ?15 0 v operating current 7 @ 250 ksps throughput avdd with internal reference 8 8.5 ma with internal reference disabled 8 6.1 ma dvdd 4 ma ovdd 0.1 ma vcc vcc = 15 v, with internal reference buffer 1.4 ma vcc = 15 v 0.8 ma vee vee = ?15 v 0.7 ma power dissipation @ 250 ksps throughput with internal reference 8 94 120 mw with internal reference disabled 8 73 100 mw in power-down mode 9 pd = high 10 w temperature range 10 specified performance t min to t max ?40 +85 c 1 in all input ranges, the input current scales wi th throughput. see the analog inputs section. 2 linearity is tested using endpoints, not best fit. all linearity is tested with an external 5 v reference. 3 lsb means least significant bit. all specifications in lsb do not include the error contributed by the reference. 4 all specifications in decibels are referred to a full-scale range input, fsr. tested with an input signal at 0.5 db below full -scale, unless othe rwise specified. 5 conversion results are available imme diately after completed conversion. 6 4.75 v or v ref ? 0.1 v, whichever is larger. 7 tested in parallel reading mode. 8 with internal reference, pdref = pdbuf = low; with internal reference disabled, pdref = pdbuf = high. with internal reference buffer, pdbuf = low. 9 with all digital inputs forced to ovdd. 10 consult sales for extended temperature range.
ad7631 rev. a | page 5 of 32 timing specifications avdd = dvdd = 5 v; ovdd = 2.7 v to 5.5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; all specifications t min to t max , unless otherwise noted. table 3. parameter symbol min typ max unit conversion and reset (see figure 35 and figure 36 ) convert pulse width t 1 10 ns time between conversions t 2 4.0 s cnvst low to busy high delay t 3 35 ns busy high all modes (except master serial read after convert) t 4 1.68 s aperture delay t 5 2 ns end of conversion to busy low delay t 6 10 ns conversion time t 7 1.68 s acquisition time t 8 2.32 ns reset pulse width t 9 10 ns parallel interface modes (see figure 37 and figure 39 ) cnvst low to data valid delay t 10 1.65 s data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 2 15 ns master serial interface modes 1 (see figure 41 and figure 42 ) cs low to sync valid delay t 14 10 ns cs low to internal sdclk valid delay 1 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay, read during convert t 17 530 ns sync asserted to sdclk first edge delay t 18 3 ns internal sdclk period 2 t 19 30 45 ns internal sdclk high 2 t 20 15 ns internal sdclk low 2 t 21 10 ns sdout valid setup time 2 t 22 4 ns sdout valid hold time 2 t 23 5 ns sdclk last edge to sync delay 2 t 24 5 ns cs high to sync high-z t 25 10 ns cs high to internal sdclk high-z t 26 10 ns cs high to sdout high-z t 27 10 ns busy high in master serial read after convert 2 t 28 see table 4 cnvst low to sync delay, read after convert t 29 1.5 s sync deasserted to busy low delay t 30 25 ns slave serial/serial configuration interface modes 1 (see figure 44 , figure 45 , and figure 47 ) external sdclk, scclk setup time t 31 5 ns external sdclk active edge to sdout delay t 32 2 18 ns sdin/scin setup time t 33 5 ns sdin/scin hold time t 34 5 ns external sdclk/scclk period t 35 25 ns external sdclk/scclk high t 36 10 ns external sdclk/scclk low t 37 10 ns 1 in serial interface modes, the sync, sdsclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 2 in serial master read during co nvert mode. see table 4 for serial master read after convert mode.
ad7631 rev. a | page 6 of 32 table 4. serial clock timings in master read after convert mode divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sdclk first edge delay minimum t 18 3 20 20 20 ns internal sdclk period minimum t 19 30 60 120 240 ns internal sdclk period maximum t 19 45 90 180 360 ns internal sdclk high minimum t 20 15 30 60 120 ns internal sdclk low minimum t 21 10 25 55 115 ns sdout valid setup time minimum t 22 4 20 20 20 ns sdout valid hold time minimum t 23 5 8 35 90 ns sdclk last edge to sync delay minimum t 24 5 7 35 90 ns busy high width maximum t 28 2.55 3.40 5.00 8.20 s notes 1. in serial interface modes, the sync, sdclk, and sdout are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 1.6ma i ol 500a i oh 1.4v to output pin c l 60pf 0 6588-002 figure 2. load circuit for digital interface timing, sdout, sync, and sdclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay 06588-003 figure 3. voltage reference levels for timing
ad7631 rev. a | page 7 of 32 absolute maximum ratings table 5. parameter rating analog inputs/outputs in+ 1 , in? 1 to agnd vee ? 0.3 v to vcc + 0.3 v ref, refbufin, temp, refgnd to agnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgnd, ognd 0.3 v supply voltages avdd, dvdd, ovdd ?0.3 v to +7 v avdd to dvdd, avdd to ovdd 7 v dvdd to ovdd 7 v vcc to agnd, dgnd C0.3 v to +16.5 v vee to gnd +0.3 v to ?16.5 v digital inputs ?0.3 v to ovdd + 0 .3 v pdref, pdbuf 20 ma internal power dissipation 2 700 mw internal power dissipation 3 2.5 w junction temperature 125c storage temperature range ?65c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 see the analog inputs section. 2 specification is for the device in free air: 48-lead lfqp; ja = 91c/w and jc = 30c/w. 3 specification is for the device in free air: 48-lead lfcsp; ja = 26c/w.
ad7631 rev. a | page 8 of 32 pin configuration and fu nction descriptions pdbuf pdref refbufin temp avdd in+ agnd vee vcc in? refgnd ref d6/ext/int d7/invsync d8/invsclk d9/rdc/sdin ognd ovdd dvdd dgnd d10/sdout d11/sdclk d12/sync d13/rderror agnd avdd mode0 mode1 d0/ob/2c d1/a0 d3 d4/divsclk[0] d5/divsclk[1] ognd ognd bipolar cnvst pd reset cs rd ten busy d17/sccs d16/scclk d15/scin d14/hw/sw 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 30 31 32 36 29 28 27 25 26 2 3 4 7 6 5 1 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 pin 1 ad7631 top view (not to scale) d2/a1 06588-004 notes 1. for the lead frame chip scale package (lfcsp), the exposed pad should be connected to vee. this connection is not required to meet the electric a l performances. figure 4. pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1, 42 agnd p analog power ground pins. ground reference point for all analog i/o. all analog i/o should be referenced to agnd and should be connected to the analog ground plane of the system. in addition, the agnd, dgnd, and ognd voltages should be at the same potential. 2, 44 avdd p analog power pins. nominally 4.75 v to 5. 25 v and decoupled with 10 f and 100 nf capacitors. 3, 4 mode[0:1] di data input/output interface mode selection. interface mode mode1 mode0 description 0 low low 18-bit interface 1 low high 16-bit interface 2 high low 8-bit (byte) interface 3 high high serial interface 5 d0/ob/ 2c di/o 2 in 18-bit parallel mode, this output is used as bit 0 of the parallel por t data output bus, and the data coding is straight binary. in all other modes, this pin allows the choice of straight binary or twos complement. when ob/ 2c = high, the digital output is straight binary. when ob/ 2c = low, the msb is inverted resulting in a twos complement output from its internal shift register. 6, 7, 17 ognd p input/output interface digital power ground. ground reference point for digital outputs. should be connected to the system digital ground idea lly at the same potential as agnd and dgnd. 8 d1/a0 di/o when mode[1:0] = 0, this pin is bit 1 of the paralle l port data output bus. in all other modes, this input pin controls the form in which data is output as shown in table 7 . 9 d2/a1 di/o when mode[1:0] = 0, this pin is bit 2 of the parallel port data output bus. when mode[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in table 7 . 10 d3 do when mode[1:0] = 0, 1, or 2, this output is used as bit 3 of the parallel port data output bus. this pin is always an output, regardless of the interface mode.
ad7631 rev. a | page 9 of 32 pin no. mnemonic type 1 description 11, 12 d[4:5] or di/o when mode[1:0] = 0, 1, or 2, these pins are bit 4 and bit 5 of the parallel port data output bus. divsclk[0:1] when mode[1:0] = 3, serial data clock division selection. when using serial master read after convert mode (ext/ int = low, rdc/sdin = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. in other serial modes, thes e pins are high impedance outputs. 13 d6 or do/i when mode[1:0] = 0, 1, or 2, this output is used as bit 6 of the para llel port data output bus. ext/ int when mode[1:0] = 3, serial data clock source select. in serial mode, this inp ut is used to select the internally generated (master) or the external ( slave) serial data clock for the ad7631 output data. when ext/ int = low (master mode), the internal serial data clock is selected on sdclk output. when ext/ int = high (slave mode), the output data is synchronized to an external clock signal (gated by cs ) connected to the sdclk input. 14 d7 or di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 7 of the parallel port data output bus. invsync when mode[1:0] = 3, serial data invert sync select. in serial master mode (mode[1:0] = 3, ext/ int = low), this input is used to select the active state of the sync signal. when invsync = low, sync is active high. when invsync = high, sync is active low. 15 d8 or di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 8 of the para llel port data output bus. invsclk when mode[1:0] = 3, invert sdclk/scclk select. this input is used to invert both sdclk and scclk. when invsclk = low, the rising edge of sdclk/scclk are used. when invsclk = high, the falling edge of sdclk/scclk are used. 16 d9 or di/o when mode[1:0] = 0, 1, or 2, this output is used as bit 9 of the parall el port data output bus. rdc or when mode[1:0] = 3, serial data read during co nvert. in serial master mode (mode[1:0] = 3, ext/ int = low), rdc is used to select the read mode. see the section. when rdc = low, the current result is read af ter conversion. note the maximum throughput is not attainable in this mode. when rdc = high, the previous conversion result is read during the current conversion. master serial interface sdin when mode[1:0] = 3, serial data in. in serial slav e mode (mode[1:0] = 3, ext/ int = high), sdin can be used as a data input to daisy-chain the conversi on results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 16 sdclk periods after the initiation of the read sequence. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface 2.5 v, 3 v, or 5 v and decoupled with 10 f and 100 nf capacitors. 19 dvdd p digital power. nominally at 4.75 v to 5.25 v and decoupled with 10 f and 100 nf capacitors. can be supplied from avdd. 20 dgnd p digital power ground. ground reference point for di gital outputs. should be connected to system digital ground ideally at the same potential as agnd and ognd. 21 d10 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 10 of the parallel port data output bus. sdout when mode[1:0] = 3, serial data outp ut. in all serial modes, this pin is used as the se rial data output synchronized to sdclk. conversion results are stored in an on-chip register. the ad7631 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . when ext/ int = low (master mode), sdout is valid on both edges of sdclk. when ext/ int = high (slave mode): when invsclk = low, sdout is updated on sdclk rising edge. when invsclk = high, sdout is updated on sdclk falling edge. 22 d11 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 11 of the parallel port data output bus. sdclk when mode[1:0] = 3, serial data clock. in all serial modes, this pin is used as the serial data clock input or output, dependent on the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin.
ad7631 rev. a | page 10 of 32 pin no. mnemonic type 1 description 23 d12 or do when mode[1:0] = 0, 1, or 2, this output is used as bit 12 of the parallel port data output bus. sync when mode[1:0] = 3, serial data frame synchroniz ation. in serial master mode (mode[1:0] = 3, ext/ int = low), this output is used as a digital o utput frame synchronization for use with the internal data clock. when a read sequence is initiated and invsync = lo w, sync is driven high and remains high while the sdout output is valid. when a read sequence is initiated and invsync = high, sync is driven low and remains low while the sdout output is valid. 24 d13 or do when mode[1:0] = 0, 1, or 2, this output is used as bit 13 of the parallel port data output bus. rderror when mode[1:0] = 3, serial data read error. in serial slave mode (mode[1:0] = 3, ext/ int = high), this output is used as an incomplete data read error flag. if a data read is started and not completed when the current conversion is completed, the curr ent data is lost and rderror is pulsed high. 25 d14 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 14 of the parallel port data output bus. hw/ sw when mode[1:0] = 3, serial configuration hardware/s oftware select. in serial mode, this input is used to configure the ad7631 by hardware or software. see the hardware configuration section and software configuration section. when hw/ sw = low, the ad7631 is configured through software using the serial configuration register. when hw/ sw = high, the ad7631 is configured through dedicated hardware input pins. 26 d15 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 15 of the parallel port data output bus. scin when mode[1:0] = 3, serial configuration data in put. in serial software configuration mode (hw/ sw = low), this input is used to serially write in, msb first, the configuration data into the serial configuration register. the data on this input is latched with scclk. see the section. software configuration 27 d16 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 16 of the parallel port data output bus. scclk when mode[1:0] = 3, serial configuration clock. in serial software configuration mode (hw/ sw = low) this input is used to clock in th e data on scin. the active edge where the data scin is updated depends on the logic state of the invsclk pin. see the section. software configuration 28 d17 or di/o when mode[1:0] = 0, 1, or 2, this outp ut is used as bit 17 of the parallel port data output bus. sccs when mode[1:0] = 3, serial configuration chip select. in serial software configuration mode (hw/ sw = low), this input enables the serial configuration port. see the section. software configuration 29 busy do busy output. transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shif t register. the falling edge of busy can be used as a data-ready clock signal. note that in mast er read after convert mode (mode[1:0] = 3, ext/ int = low, rdc = low) the busy time changes according to . table 4 30 ten di 2 input range select. used in conjunction with bipolar per the following. input range (v) bipolar ten 0 to 5 low low 0 to 10 low high 5 high low 10 high high 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock in slave se rial mode (not used for serial configurable port). 33 reset di reset input. when high, reset the ad7631. current conversion, if any, is aborted. the falling edge of reset resets the data outp uts to all zeros (with ob/ 2c = high) and clears the configuration register. see the section. if not used, this pin can be tied to ognd. digital interface 34 pd di 2 power-down input. when pd = high, power down the adc. power consumption is reduced and conversions are inhibited after the current one is completed. the digital interface remains active during power down. 35 cnvst di conversion start. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. 36 bipolar di 2 input range select. see description for pin 30.
ad7631 rev. a | page 11 of 32 pin no. mnemonic type 1 description 37 ref ao/i reference input/output. when pdref/pdbuf = low, the internal reference and buffer are enabled producing 5 v on this pin. when pdref/pdbuf = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to avdd volts. decoupling with at least a 22 f capacitor is required with or without th e internal reference and buffer. see the voltage reference input/output section. 38 refgnd ai reference input analog grou nd. connected to analog ground plane. 39 in? ai analog input. referenced to in+. in the 0 v to 5 v input range, in? is between 0 v and v ref v centered about v ref /2. in the 0 v to 10 v range, in? is between 0 v and 2 v ref v centered about v ref . in the 5 v and 10 v ranges, in? is true bipolar up to 2 v ref v (5 v range) or 4 v ref v (10 v range) and centered about 0 v. in all ranges, in? must be driven 180 out of phase with in+. 40 vcc p high voltage positive supply. normally +7 v to +15 v. 41 vee p high voltage negative supply. normally 0 v to ?15 v (0 v in unipolar ranges). 43 in+ ai analog input. referenced to in?. in the 0 v to 5 v input range, in+ is between 0 v and v ref v centered about v ref /2. in the 0 v to 10 v range, in+ is between 0 v and 2 v ref v centered about v ref . in the 5 v and 10 v ranges, in+ is true bipolar up to 2 v ref v (5 v range) or 4 v ref v (10 v range) and centered about 0 v. in all ranges, in+ must be driven 180 out of phase with in?. 45 temp ao temperature sensor analog output. when the internal reference is enabled (pdref = pdbuf = low), this pin outputs a voltage proportional to the temperature of the ad7631. see the voltage reference input/output section. 46 refbufin ai reference buffer input. when using an external reference with the internal reference buffer (pdbuf = low, pdref = high), applying 2.5 v on this pi n produces 5 v on the ref pin. see the voltage reference input/output section. 47 pdref di internal reference power-down input. when low, the internal reference is enabled. when high, the internal reference is powered down, and an external reference must be used. 48 pdbuf di internal reference buffer power-down input. when low, the buffer is enabled (must be low when using internal reference). when high, the buffer is powered down. 49 epad 3 nc exposed pad. the exposed pad is not connected intern ally. it is recommended that the pad be soldered to vee. 1 ai = analog input; ai/o = bidirectional analog; ao = analog output; di = digital input; di/o = bidirectional digital; do = dig ital output; p = power, nc = no internal connection. 2 in serial configuration mode (mode[1:0] = 3, hw/ sw = low), this input is programmed with the serial configuration register an d this pin is a dont care. see the hardware configuration section and the software configuraion section. 3 lfcsp_vq package only. table 7. data bus interface definition mode mode1 mode0 d0/ob/ 2c d1/a0 d2/a1 d[3] d[4:9] d[10:11] d[12:15] d[16:17] description 0 0 0 r[0] r[1] r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 18-bit parallel 1 0 1 ob/ 2c a0 = 0 r[2] r[3] r[4:9] r[10:11] r[12:15] r[16:17] 16-bit high word 1 0 1 ob/ 2c a0 = 1 r[0] r[1] all zeros 16-bit low word 2 1 0 ob/ 2c a0 = 0 a1 = 0 all high-z r[10:11] r[12:15] r[16:17] 8-bit high byte 2 1 0 ob/ 2c a0 = 0 a1 = 1 all high-z r[2:3] r[4:7] r[8:9] 8-bit midbyte 2 1 0 ob/ 2c a0 = 1 a1 = 0 all high-z r[0:1] all zeros 8-bit low byte 2 1 0 ob/ 2c a0 = 1 a1 = 1 all high-z all zeros r[0:1] 8-bit low byte 3 1 1 ob/ 2c all high-z serial interface serial interface
ad7631 rev. a | page 12 of 32 typical performance characteristics avdd = dvdd = 5 v; ovdd = 5 v; vcc = 15 v; vee = ?15 v; v ref = 5 v; t a = 25c. 06588-005 code inl (lsb) 2.5 2.0 1.5 1.0 0.5 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 65536 0 131072 196608 262144 positive inl = 1.15 lsb negative inl = ?0.94 lsb f s = 250ksps figure 5. integral nonlinearity vs. code, bipolar 10 v range 06588-006 inl distribution (lsb) number of units 0 10 20 30 40 50 60 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 negative inl positive inl figure 6. integral nonlinearity distribution, unipolar 10 v range (86 devices) 70000 0 1fffe 20008 counts code in hex 20000 20002 20004 20006 60000 50000 40000 20000 30000 10000 06588-007 = 0.80 00 25 34164 2172 20 00 1997 32769 59925 figure 7. histogram of 261,120 conversions of a dc input at the code center, bipolar 5 v range 06588-008 code dnl (lsb) 2.5 2.0 1.5 1.0 0.5 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 65536 0 131072 196608 262144 positive dnl = 0.68 lsb negative dnl = ?0.75 lsb f s = 250ksps figure 8. differential nonlinearity vs. code, bipolar 10 v range 06588-009 dnl distribution (lsb) number of units 0 10 20 30 40 50 60 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 negative dnl positive dnl figure 9. differential nonlinearity distribution, bipolar 5 v range (86 devices) counts code in hex 20006 1fffc 1fffe 20000 20002 20004 60000 0 50000 40000 30000 20000 10000 06588-010 00 = 0.75 56811 54874 005 6901 294 349 11838 figure 10. histogram of 261,120 conversions of a dc input at the code transition, bipolar 5 v range
ad7631 rev. a | page 13 of 32 0 ?180 amplitude (db of full scale) 0 frequency (khz) 200 250 300 50 100 150 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 f s = 250ksps f in = 20.1khz snr = 98.3db thd = ?116.8db sfdr = 121db sinad = 97.8db 06588-011 figure 11. fft 20 khz, bipolar 5 v range, internal reference enob (bits) 80 82 84 86 88 90 92 94 96 98 100 1 10 100 1000 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 snr sinad enob 06588-012 frequency (khz) snr, sinad (db) figure 12. snr, sinad, and enob vs. frequency, unipolar 5 v range 0 6588-013 temperature (c) snr (db) 97 98 99 100 101 102 103 ?55 ?35 ?15 5 25 45 65 85 105 125 0v to 10v 0v to 5v 5v 10v figure 13. snr vs. temperature 06588-014 input level (db) snr, sinad referred to full scale (db) 100.0 100.5 101.0 101.5 102.0 102.5 103.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10v 5v 0v to 10v 0v to 5v snr sinad figure 14. snr and sinad vs. input level (referred to full scale) sfdr (db) 1 10 100 1000 06588-015 frequency (khz) thd, harmonics (db) 0 20 40 60 80 100 120 140 sfdr thd second harmonic third harmonic ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 figure 15. thd, harmonics, and sfdr vs. frequency, unipolar 5 v range 06588-016 temperature (c) sinad (db) ?55 ?35 ?15 5 25 45 65 85 105 125 97 98 99 100 101 102 103 0v to 10v 0v to 5v 5v 10v figure 16. sinad vs. temperature
ad7631 rev. a | page 14 of 32 06588-017 temperature (c) thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 ?132 ?128 ?124 ?120 ?116 ?112 ?108 ? 104 0v to 10v 5v 10v 0v to 5v figure 17. thd vs. temperature ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 20 ?55 ?35 ?15 5 25 45 65 85 105 125 zero/offset error positive full-scale error negative full-scale error temperature (c) zero/offset error, full-scale error (lsb) 0 6588-018 figure 18. zero/offset error, positive and negative full-scale error vs. temperature, all normalized to 25c 60 0 08 reference drift (ppm/c) number of units 50 40 30 20 10 1234567 06588-019 figure 19. reference voltage temperature coefficient distribution (247 devices) 06588-020 temperature (c) sfdr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 104 108 112 116 120 124 128 132 0v to 10v 0v to 5v 5v 10v figure 20. sfdr vs. temperature (excludes harmonics) 5.0080 4.9920 ?55 125 temperature (c) v ref (v) ?35 ?15 5 25 45 65 85 105 06588-021 4.9940 4.9960 4.9980 5.0000 5.0020 5.0040 5.0060 figure 21. typical reference voltage output vs. temperature (3 devices) 0.001 0.01 0.1 1 10 100 1000 10000 100000 10 100 1000 10000 100000 1000000 ovdd dvdd avdd pdref = pdbuf = high vcc +15v vee ?15v 0 6588-022 sampling rate (sps) operating currents (a) figure 22. operating currents vs. sample rate
ad7631 rev. a | page 15 of 32 700 0 ?55 105 temperature (c) power-down operating currents (na) 600 500 400 300 200 100 ?35 ?15 5 25 45 65 85 vee, ?15v vcc, +15v dvdd ovdd avdd pd = pdbuf = pdref = high 06588-023 figure 23. power-down operating currents vs. temperature 0 5 10 15 20 25 30 35 40 45 50 0 50 100 150 200 c l (pf) t 12 delay (ns) ovdd = 2.7v @ 25c ovdd = 2.7v @ 85c ovdd = 5v @ 85c ovdd = 5v @ 25c 0 6588-024 figure 24. typical delay vs. load capacitance c l
ad7631 rev. a | page 16 of 32 terminology least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that can be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is n inp-p v vlsb 2 )( = integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full-scale through positive full- scale. the point used as negative full-scale occurs a ? lsb before the first code transition. positive full-scale is defined as a level 1? lsbs beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. bipolar zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar offset error the first transition should occur at a level ? lsb above analog ground. the unipolar offset error is the deviation of the actual transition from that point. full-scale error the last transition (from 11110 to 11111 in straight binary format) should occur for an analog voltage 1? lsb below the nominal full scale. the full-scale error is the deviation in lsb (or % of full-scale range) of the actual level of the last transition from the ideal level and includes the effect of the offset error. closely related is the gain error (also in lsb or % of full-scale range), which does not include the effects of the offset error. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured for an input typically at ?60 db. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious-free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad and is expressed in bits by enob = [( sinad db ? 1.76)/6.02] aperture delay aperture delay is a measure of the acquisition performance measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient resp onse the time required for the ad7631 to achieve its rated accuracy after a full-scale step function is applied to its input. reference voltage temperature coefficient the reference voltage temperature coefficient is derived from the typical shift of output voltage at 25c on a sample of parts at the maximum and minimum reference output voltage (v ref ) measured at t min , t (25c), and t max . it is expressed in ppm/c as 6 10 c25 ( ( cppm/ = )tCt()(v )minvC)maxv )(tcv min max ref ref ref ref where: v ref ( max ) = maximum v ref at t min , t (25c), or t max . v ref ( min ) = minimum v ref at t min , t (25c), or t max . v ref (25 c ) = v ref at 25c. t max = +85c. t min = C40c.
ad7631 rev. a | page 17 of 32 theory of operation sw+ comp sw? in+ ref refgnd lsb msb 131,072c 65,536c 4c 2c c c control logic switches control busy output code cnvst in? 4c 2c c c lsb msb agnd agnd 131,072c 65,536c 06588-025 figure 25. adc simplified schematic overview the ad7631 is a very fast, low power, precise, 18-bit adc using successive approximation, capacitive digital-to-analog (cdac) architecture. the ad7631 can be configured at any time for one of four input ranges with inputs in parallel and serial hardware modes or by a dedicated write-only, spi-compatible interface via a configuration register in serial software mode. the ad7631 uses analog devices patented i cmos high voltage process to accommodate 0 v to +5 v (10 v p-p), 0 v to +10 v (20 v p-p), 5 v (20 v p-p), and 10 v (40 v p-p) input ranges on the fully differential in+ and in? inputs without the use of conventional thin films. only one acquisition cycle, t 8 , is required for the inputs to latch to the correct configuration. resetting or power cycling is not required for reconfiguring the adc. the ad7631 is capable of converting 250,000 samples per second (250 ksps) and power consumption scales linearly with throughput, making it useful for battery-powered systems. the ad7631 provides the user with an on-chip track-and-hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple, multiplexed channel applications. for unipolar input ranges, the ad7631 typically requires three supplies: vcc, avdd (which can supply dvdd), and ovdd (which can be interfaced to either 5 v, 3.3 v, or 2.5 v digital logic). for bipolar input ranges, the ad7631 requires the use of the additional vee supply. the device is housed in a pb-free, 48-lead lqfp or a tiny, 48-lead, 7 mm 7 mm lfcsp that combines space savings with flexibility. in addition, the ad7631 can be configured as either a parallel or serial spi-compatible interface. converter operation the ad7631 is a successive approximation adc based on a charge redistribution dac. figure 25 shows the simplified schematic of the adc. the cdac consists of two identical arrays of 18 binary weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the comparators input are connected to agnd via sw+ and sw?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on in+ and in? inputs. a conversion phase is initiated once the acquisition phase is complete and the cnvst input goes low. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between the inputs (in+ and in?) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between refgnd and ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4 through v ref /262,144). the control logic toggles these switches, starting with the msb first, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings the busy output low.
ad7631 rev. a | page 18 of 32 transfer functions using the d0/ob/ 2c digital input or via the configuration register, except in 18-bit parallel interface mode, the ad7631 offers two output codings: straight binary and twos complement. see and for the ideal transfer characteristic and digital output codes for the different analog input ranges, v in . note that when using the configuration register, the d0/ob/ figure 26 table 8 2c input is a dont care and should be tied to either high or low. 000...000 000...001 000...010 111...101 111...110 111...111 adc code (straight binary) analog input +fsr ? 1.5 lsb +fsr ?1lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 06588-026 figure 26. adc ideal transfer function typical connection diagram figure 27 shows a typical connection diagram for the ad7631 using the internal reference, serial data interface, and serial configuration port. different circuitry from that shown in figure 27 is optional and is discussed in the following sections. table 8. output codes and ideal input voltages v ref = 5 v digital output code description v in = 0 v to 5 v (10 v p-p) v in = 0 v to 10 v (20 v p-p) v in = 5 v (20 v p-p) v in = 10 v (40 v p-p) straight binary twos complement fsr ? 1 lsb +4.999962 v +9.999924 v +9.999924 v +19.999847 v 0x3ffff 1 0x1ffff 1 fsr ? 2 lsb +4.999924 v +9.999847 v +9.999847 v +19.999695 v 0x3fffe 0x1fffe midscale + 1 lsb +38.15 v ?76.29 v ?76.29 v +152.59 v 0x20001 0x00001 midscale 0 v 0 v 0 v 0 v 0x20000 0x00000 midscale ? 1 lsb ?38.15 v ?76.29 v ?76.29 v ?152.59 v 0x1ffff 0x3ffff ?fsr + 1 lsb ?4.999962 v ?9.999924 v ?9.999924 v ?19.999847 v 0x00001 0x20001 ?fsr ?5 v ?10 v ?10 v ?20 v 0x00000 2 0x20000 2 1 this is also the code fo r overrange analog input. 2 this is also the code fo r underrange analog input.
ad7631 rev. a | page 19 of 32 rd cs 100nf 100nf avdd 10f 100nf 10 ? agnd dgnd dvdd ovdd ognd cnvst busy sdout sdclk reset pd refbufin d clock ad7631 digital interface supply (2.5v, 3.3v, or 5v) analog supply (5v) ovdd digital supply (5v) in+ in? note 5 analog input+ c c 2.7nf u1 note 1 mode[1:0] d0/ob/2c refgnd ref pdbuf pdref 100nf note 3 note 4 note 3 note 7 10f 10f c ref 22f notes 1. analog inputs are differential (antiphase). see analog inputs section. 2. the ad8021 is recommended. see driver amplifier choice section. 3. the configuration shown is using the internal reference. see voltage reference input/output section. 4. a 22f ceramic capacitor (x5r, 1206 size) is recommended (for example, panasonic ecj4yb1a226m). see voltage reference input/output section. 5. optional, see power supplies section. 6. the vcc and vee supplies should be vcc = [vin(max) + 2v] and vee = [vin(min) ? 2v] for bipolar input ranges. for unipolar input ranges, vee can be 0v. see power supplies section. 7. optional low jitter cnvst, see conversion control section. 8. a separate analog and digital ground plane is recommended, connected together directly under the adc. see layout guidelines section. analog input? note 2 vcc vee 10f 100nf +7v to +15.75v supply 10f 100nf ?7v to ?15.75v supply note 6 hw/sw sccs scclk scin bipolar ten serial port 1 serial port 2 c c 2.7nf u1 note 2 06588-027 15 ? 15 ? 33 ? agnd dgnd note 8 microconverter ? / microprocessor/ dsp figure 27. typical connection diagram shown with serial interface and serial programmable port analog inputs input range selection in parallel mode and serial hardware mode, the input range is selected by using the bipolar (bipolar) and ten (10 v range) inputs. see table 6 for pin details and the hardware configuration section and the software configuration section for programming the mode selection with either pins or the configuration register. note that when using the configuration register, the bipolar and ten inputs are dont cares and should be tied high or low. input structure figure 28 shows an equivalent circuit for the input structure of the ad7631. d1 r in c in d2 in+ or in? vee vcc c pin agnd d3 d4 avdd 0 v to 5v range only 0 6588-028 figure 28. simplified analog input
ad7631 rev. a | page 20 of 32 the four diodes, d1 to d4, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v, because this causes the diodes to become forward-biased and to start conducting current. these diodes can handle a forward- biased current of 120 ma maximum. for instance, these conditions could eventually occur when the input buffers u1 supplies are different from avdd, vcc, and vee. in such a case, an input buffer with a short-circuit current limitation can be used to protect the part although most op amps short-circuit current is <100 ma. note that d3 and d4 are only used in the 0 v to 5 v range to allow for additional protection in applications that are switching from the higher voltage ranges. this analog input structure of the ad7631 is a true differential structure allowing the sampling of the differential signal between in+ and in?. by using this differential input, small signals common to both inputs are rejected, as shown in figure 29 , which represents the typical cmrr over frequency. 120 0 1 10000 frequency (khz) cmrr (db) 100 80 60 40 20 10 100 1000 06588-029 0v to 10v 5v 0v to 5v 10v figure 29. analog input cmrr vs. frequency during the acquisition phase for ac signals, the impedance of the analog inputs, in+ and in?, can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 5 k and is a lumped component comprised of serial resistors and the on resistance of the switches. c in is primarily the adc sampling capacitor and, depending on the input range selected, is typically 48 pf in the 0 v to 5 v range, typically 24 pf in the 0 v to 10 v and 5 v ranges, and typically 12 pf in the 10 v range. during the conversion phase, when the switches are opened, the input impedance is limited to c pin . because the input impedance of the ad7631 is very high, it can be directly driven by a low impedance source without gain error. to further improve the noise filtering achieved by the ad7631 analog input circuit, an external, one-pole rc filter between the amplifiers outputs and the adc analog inputs can be used, as shown in figure 27 . however, large source impedances significantly affect the ac performance, especially the thd. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency, as shown in figure 30 . ?130 ?110 ?90 ? 70 0 25 50 75 100 15? 33 ? 100? 200? 06588-030 frequency (khz) thd (db) figure 30. thd vs. analog input frequency and source resistance d river amplifier choice although the ad7631 is easy to drive, the driver amplifier must meet the following requirements: x for multichannel, multiplexed applications, the driver amplifier and the ad7631 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 18-bit level (0.0004%). for the amplifier, settling at 0.1% to 0.01% is more commonly specified. this differs significantly from the settling time at a 18-bit level and should be verified prior to driver selection. the ad8021 op amp combines ultralow noise with high gain bandwidth and meets this settling time requirement even when used with gains of up to 13. x the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7631. the noise coming from the driver is filtered by the external, 1-pole, low-pass filter, as shown in figure 27 . the snr degradation due to the amplifier is s s 2 3db 2 3db 2 )( 2 )( 2 log20 n n nadc nadc loss nef nef v v snr where: v nadc is the noise of the adc, which is 20 10 22 2 snr inp-p nadc v v f C3db is the cutoff frequency of the input filter (3.9 mhz).
ad7631 rev. a | page 21 of 32 n is the noise factor of the amplifier (1 in buffer configuration). e n+ and e n? are the equivalent input voltage noise densities of the op amps connected to in+ and in?, in nv/hz. this approximation can be utilized when the resistances used around the amplifiers are small. if larger resistances are used, their noise contributions should also be root-sum squared. ? the driver needs to have a thd performance suitable to that of the ad7631. figure 15 shows the thd vs. frequency that the driver should exceed. the ad8021 meets these requirements and is appropriate for almost all applications. the ad8021 needs a 10 pf external compensation capacitor that should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. the ad8022 can also be used when a dual version is needed and a gain of 1 is present. the ad829 is an alternative in applications where high frequency performance (above 100 khz) is not required. in applications with a gain of 1, an 82 pf compensation capacitor is required. the ad8610 is an option when low bias current is needed in low frequency applications. because the ad7631 uses a large geometry, high voltage input switch, the best linearity performance is obtained when using the amplifier at its maximum full power bandwidth. gaining the amplifier to make use of the more dynamic range of the adc results in increased linearity errors. for applications requiring more resolution, the use of an additional amplifier with gain should precede a unity follower driving the ad7631. see table 9 for a list of recommended op amps. table 9. recommended driver amplifiers amplifier typical application ad829 15 v supplies, very low noise, low frequency ad8021 12 v supplies, very low noise, high frequency ad8022 12 v supplies, very low noise, high frequency, dual ada4922-1 12 v supplies, low noise, high frequency, single-ended-to-differential driver ad8610 / ad8620 13 v supplies, low bias current, low frequency, single/dual single-to-differential driver for single-ended sources, a single-to-differential driver, such as the ada4922-1 , can be used because the ad7631 needs to be driven differentially. the 1-pole filter using r = 15 and c = 2.7 nf provides a corner frequency of 3.9 mhz. 06588-031 analog input in+ in? ad7631 ref 10 f 15 ? 15 ? 100nf 2.7nf 2.7nf u2 r1 r2 ada4922-1 out+ vcc vee out? in ref r f r g figure 31. single-to-differential driver using the ada4922-1 for unipolar 5 v and 10 v input ranges, the internal (or external) reference source can be used to level shift u2 for the correct input span. if using an external reference, the values for r1/r2 can be lowered to reduce resistive johnson noise (1.29e ? 10 r). for the bipolar 5 v and 10 v input ranges, the reference connection is not required because the common-mode voltage is 0 v. see table 10 for the different input ranges for r1/r2. table 10.r1/r2 configuration input range (v) r1 () r2 () common-mode voltage (v) 5 2.5 k 2.5 k 2.5 10 2.5 k open 5 5, 10 100 0 this circuit can also be made discretely, and thus more flexible, using any of the recommended low noise amplifiers in tabl e 9 . again, to preserve the snr of the converter, the resistors r f and r g should be kept low. voltage reference input/output the ad7631 allows the choice of either a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. the internal reference of the ad7631 provides excellent performance and can be used in almost all applications. however, the linearity performance is guaranteed only with an external reference. internal reference (ref = 5 v)(pdref = low, pdbuf = low) to use the internal reference, the pdref and pdbuf inputs must be low. this enables the on-chip band gap reference, buffer, and temp sensor resulting in a 5.00 v reference on the ref pin. the internal reference is temperature-compensated to 5.000 v 35 mv. the reference is trimmed to provide a typical drift of 3 ppm/c. this typical drift characteristic is shown in figure 19 .
ad7631 rev. a | page 22 of 32 external 2.5 v reference and internal buffer (ref = 5 v) (pdref = high, pdbuf = low) to use an external reference with the internal buffer, pdref should be high and pdbuf should be low. this powers down the internal reference and allows the 2.5 v reference to be applied to refbufin producing 5 v on the ref pin. the internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications to avoid reference coupling amongst the different converters. external 5 v reference (pdref = high, pdbuf = high) to use an external reference directly on the ref pin, pdref and pdbuf should both be high. pdref and pdbuf power down the internal reference and the internal reference buffer, respectively. for improved drift performance, an external reference, such as the adr445 or adr435 , is recommended. reference decoupling whether using an internal or external reference, the ad7631 voltage reference input (ref) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a low esr capacitor connected to ref and refgnd with minimum parasitic inductance. a 22 f (x5r, 1206 size) ceramic chip capacitor (or 47 f low esr tantalum capacitor) is appropriate when using either the internal reference or the adr445 / adr435 external reference. the placement of the reference decoupling is also important to the performance of the ad7631. the decoupling capacitor should be mounted on the same side as the adc right at the ref pin with a thick pcb trace. the refgnd should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias. for applications that use multiple ad7631s or other pulsar devices, it is more effective to use the internal reference buffer to buffer the external 2.5 v reference voltage. the voltage reference temperature coefficient (tc) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the tc. for instance, a 4 ppm/c tc of the reference changes full scale by 1 lsb/c. temperature sensor the temp pin measures the temperature of the ad7631. to improve the calibration accuracy over the temperature range, the output of the temp pin is applied to one of the inputs of the analog switch (such as adg779 ), and the adc itself is used to measure its own temperature. this configuration is shown in figure 32 . adg779 c c analog input ad7631 in+ temperature sensor temp 06588-032 figure 32. use of the temperature sensor power supplies t he ad7631 uses five sets of power supply pins: ? avdd: analog 5 v core supply ? vcc: analog high voltage positive supply ? vee: high voltage negative supply ? dvdd: digital 5 v core supply ? ovdd: digital input/output interface supply core supplies the avdd and dvdd supply the ad7631 analog and digital cores, respectively. sufficient decoupling of these supplies is required consisting of at least a 10 f capacitor and a 100 nf capacitor on each supply. the 100 nf capacitors should be placed as close as possible to the ad7631. to reduce the number of supplies needed, the dvdd can be supplied through a simple rc filter from the analog supply, as shown in figure 27 . high voltage supplies the high voltage bipolar supplies, vcc and vee, are required and must be at least 2 v larger than the maximum input voltage. for example, if using the 10 v range, the supplies should be 12 v minimum. this allows for 40 v p-p fully differential input (10 v on each input in+ and in?). sufficient decoupling of these supplies is also required consisting of at least a 10 f capacitor and a 100 nf capacitor on each supply. for unipolar operation, the vee supply can be grounded with some slight thd performance degradation. digital output supply the ovdd supplies the digital outputs and allows direct interface with any logic working between 2.3 v and 5.25 v. ovdd should be set to the same level as the system interface. sufficient decoupling is required consisting of at least a 10 f capacitor and a 100 nf capacitor with the 100 nf placed as close as possible to the ad7631.
ad7631 rev. a | page 23 of 32 power sequencing power down the ad7631 is independent of power supply sequencing and is very insensitive to power supply variations on avdd over a wide frequency range, as shown in figure 33 . setting pd = high powers down the ad7631, thus reducing supply currents to their minimums, as shown in figure 23 . when the adc is in power-down, the current conversion (if any) is completed and the digital bus remains active. to further reduce the digital supply currents, drive the inputs to ovdd or ognd. 30 35 40 45 50 55 60 65 70 75 1 10 100 1000 10000 0 6588-033 frequency (khz) psrr (db) power-down can also be programmed with the configuration register. see the software configuration section for details. note that when using the configuration register, the pd input is a dont care and should be tied to either high or low. conversion control the ad7631 is controlled by the cnvst input. a falling edge on cnvst is all that is necessary to initiate a conversion. a detailed timing diagram of the conversion process is shown in . once initiated, it cannot be restarted or aborted, even by the power-down input, pd, until the conversion is complete. the figure 35 cnvst signal operates independently of cs and rd signals. figure 33. avdd psrr vs. frequency power dissipation vs. throughput busy mode convert acquire acquire convert cnvst t 1 t 2 t 4 t 3 t 5 t 6 t 7 t 8 0 6588-035 in impulse mode, the ad7631 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced (see figure 34 ). this feature makes the ad7631 ideal for very low power, battery-operated applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, drive the digital inputs close to the power rails, that is, ovdd and ognd. figure 35. basic conversion timing 1 10 100 1000 1 10 100 1000 10000 100000 1000000 pdref = pdbuf = high 0 6588-034 sampling rate (ksps) power dissipation (mw) although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot, undershoot, or ringing. the cnvst trace should be shielded with ground and a low value (such as 50 ) serial resistor termination should be added close to the output of the component that drives this line. for applications where snr is critical, the cnvst signal should have very low jitter. this can be achieved by using a dedicated oscillator for cnvst generation, or by clocking cnvst with a high frequency, low jitter clock, as shown in . figure 27 figure 34. power dissipa tion vs. sample rate
ad7631 rev. a | page 24 of 32 interfaces digital interface the ad7631 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. the serial interface is multiplexed on the parallel data bus. the ad7631 digital interface also accommodates 2.5 v, 3.3 v, or 5 v logic. in most applications, the ovdd supply pin is connected to the host system interface 2.5 v to 5.25 v digital supply. finally, by using the d0/ob/ 2c input pin, both twos complement or straight binary coding can be used, except for a 18-bit parallel interface. two signals, cs and rd , control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7631 in multicircuit applications and is held low in a single ad7631 design. rd is generally used to enable the conversion result on the data bus. reset the reset input is used to reset the ad7631. a rising edge on reset aborts the current conversion (if any) and tristates the data bus. the falling edge of reset resets the ad7631 and clears the data bus and configuration register. see figure 36 for the reset timing details. t 9 t 8 reset data bus busy cnvst 0 6588-036 figure 36. reset timing parallel interface the ad7631 is configured to use the parallel interface when the mode[1:0] pins = 0, 1, or 2 for 18-/16-/8-bit interfaces, respectively, as shown in table 7 . master parallel interface data can be continuously read by tying cs and rd low, thus requiring minimal microprocessor connections. however, in this mode, the data bus is always driven and cannot be used in shared bus applications (unless the device is held in reset). details the timing for this mode. figure 37 t 1 busy data bus previous conversion data new data cnvst cs = rd = 0 t 10 t 4 t 11 t 3 06588-037 figure 37. master parallel data timing for reading (continuous read) slave parallel interface in slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in figure 38 and figure 39 , respectively. when the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. this avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion t 13 t 12 busy data bus rd cs 06588-038 figure 38. slave parallel data timing for reading (read after convert) previous conversion t 13 t 12 t 3 busy data bus cnvst, rd cs = 0 t 4 t 1 06588-039 figure 39. slave parallel data timing for reading (read during convert)
ad7631 rev. a | page 25 of 32 18-bit interface (master or slave) the 18-bit interface is selected by setting mode[1:0] = 0. in this mode, the data output is straight binary. 16-bit and 8-bit interface (master or slave) in the 16-bit (mode[1:0] = 1) and 8-bit (mode[1:0] = 2) interfaces, pin a0 and pin a1 al low a glueless interface to a 16- or 8-bit bus, as shown in figure 40 (refer to table 7 for more details). by connecting pin a0 and pin a1 to an address line(s), the data can be read in two words for a 16-bit interface or three bytes for an 8-bit interface. this interface can be used in both master and slave parallel reading modes. cs, rd a1 d[17:2] hi-z high word low word hi-z t 12 t 13 high byte a0 mid byte low byte d[17:10] t 12 hi-z hi-z t 12 0 6588-040 figure 40. 8-bit and16-bit parallel interface serial interface the ad7631 is configured to use the serial interface when mode[1:0]= 3. the ad7631 has a serial interface (spi-compatible) multiplexed on the data pins d[17:4]. data interface the ad7631 outputs 18 bits of data, msb first, on the sdout pin. this data is synchronized with the 18 clock pulses provided on the sdclk pin. the output data is valid on both the rising and falling edge of the data clock. serial configuration interface the ad7631 can only be configured through the serial configuration register in serial mode as the serial configuration pins are also multiplexed on the data pins d[17:14]. see the hardware configuration section and the software configuration section for more information. master serial interface the pins multiplexed on d[12:4] and used for master serial interface are: divsclk[1:0], ext/ int , invsync, invsclk, rdc, sdout, sdclk, and sync. internal clock (mode[1:0] = 3, ext/ int = low) the ad7631 is configured to generate and provide the serial data clock, sdclk, when the ext/ int pin is held low. the ad7631 also generates a sync signal to indicate to the host when the serial data is valid. the sdclk and the sync signals can be inverted, if desired, using the invsclk and invsync inputs, respectively. depending on the input, rdc, the data can be read during the following conversion or after each conversion. and show detailed timing diagrams of these two modes. figure 41 figure 42 read during convert (rdc = high) setting rdc = high allows the master read (previous conversion result) during conversion mode. usually, because the ad7631 is used with a fast throughput, this mode is the most recommended serial mode. in this mode, the serial clock and data switch on and off at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion decisions. in this mode, the sdclk period changes because the lsbs require more time to settle, and the sdclk is derived from the sar conversion cycle. in this mode, the ad7631 generates a discontinuous sdclk of two different periods, and the host should use an spi interface. read after convert (rdc = low, divsclk[1:0] = [0 to 3]) setting rdc = low allows the read after conversion mode. unlike the other serial modes, the busy signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer busy width (see table 4 for busy timing specifications). the divsclk[1:0] inputs control the sdclk period and sdout data rate. as a result, the maximum throughput cannot be achieved in this mode. in this mode, the ad7631 also generates a discontinuous sdclk; however, a fixed period and hosts supporting both spi and serial ports can also be used.
ad7631 rev. a | page 26 of 32 ext/int = 0 rdc/sdin = 1 invsclk = invsync = 0 d17 d16 d2 d1 d0 x 123 161718 busy sync sdclk sdout cnvst cs, rd t 23 t 18 t 15 t 14 t 17 t 3 t 22 t 16 t 1 t 25 t 26 t 24 t 27 t 19 t 20 t 21 mode[1:0] = 3 06588-041 figure 41. master serial data timing for reading (read previous conversion during convert) busy sync sdclk sdout 123 161718 d17 d16 d2 d1 d0 x rdc/sdin = 0 invsclk = invsync = 0 cnvst cs, rd ext/int = 0 t 23 t 22 t 16 t 15 t 14 t 29 t 19 t 21 t 20 t 18 t 28 t 30 t 24 t 25 t 26 t 27 t 3 mode[1:0] = 3 06588-042 figure 42. master serial data timing for reading (read after convert) slave serial interface the pins multiplexed on d[13:6] used for slave serial interface are: ext/ int , invsclk, sdin, sdout, sdclk, and rderror. external clock (mode[1:0] = 3, ext/ int = high) setting the ext/ int = high allows the ad7631 to accept an externally supplied serial data clock on the sdclk pin. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conv ersion or during the following conversion. a clock can be either normally high or normally low when inactive. for detailed timing diagrams, see and . figure 44 figure 45 while the ad7631 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result may occur. this is particularly important during the last 550 ns of the conversion phase because the ad7631 provides error correction circuitry that can correct for an improper bit decision made during the first part of the conversion phase. for this reason, it is recommended that any external clock provided is a discontinuous clock that transitions only when busy is low, or, more importantly, that it does not transition during the last 450 ns of busy high.
ad7631 rev. a | page 27 of 32 external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 44 shows the detailed timing diagrams for this method. after a conversion is completed, indicated by busy returning low, the conversion result can be read while both cs and rd are low. data is shifted out msb first with 18 clock pulses and, depending on the sdclk frequency, can be valid on the falling and rising edges of the clock. one advantage of this method is that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is the ability to read the data at any speed up to 40 mhz, which accommodates both the slow digital host interface and the fastest serial reading. daisy-chain feature in addition, in the read after convert mode, the ad7631 provides a daisy-chain feature for cascading multiple converters together using the serial data input pin, sdin. this feature is useful for reducing component count and wiring connections when desired, for instance, in isolated multiconverter applications. see figure 44 for the timing details. an example of the concatenation of two devices is shown in figure 43 . simultaneous sampling is possible by using a common cnvst signal. note that the sdin input is latched on the opposite edge of sdclk used to shift out the data on sdout (sdclk falling edge when invsclk = low). therefore, the msb of the upstream converter follows the lsb of the downstream converter on the next sdclk cycle. in this mode, the 40 mhz sdclk rate cannot be used because the sdin to sdclk setup time, t 33 , is less than the minimum time specified. (sdclk to sdout delay, t 32 , is the same for all converters when simultaneously sampled). for proper operation, the sdclk edge for latching sdin (or ? period of sdclk) needs to be 3332 sdclk ttt += 2/1 or the maximum sdclk frequency needs to be )(2 1 3332 sdclk tt f + = if not using the daisy-chain feature, the sdin input should always be tied either high or low. sdclk sdout rdc/sdin ad7631 #1 (downstream) ad7631 #2 (upstream) busy out busy busy data out sdclk rdc/sdin sdout sdclk in cnvst in cnvst cs cnvst cs cs in 0 6588-043 figure 43. two ad7631 devices in a daisy-chain configuration external clock data read during previous conversion figure 45 shows the detailed timing diagrams for this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 18 clock pulses and is valid on both the falling and rising edges of the clock. the 18 bits have to be read before the current conversion is completed; otherwise, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 40 mhz is recommended to ensure that all the bits are read during the first half of the sar conversion phase. the daisy-chain feature should not be used in this mode because digital activity occurs during the second half of the sar conversion phase likely resulting in performance degradation. external clock data read after/during conversion it is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. this method allows the full throughput and the use of a slower sdclk frequency. again, it is recommended to use a discontinuous sdclk whenever possible to minimize potential incorrect bit decisions. the use of a slower sdclk, such as 13 mhz, can be used.
ad7631 rev. a | page 28 of 32 sdin sdout d0 123 1718 busy ext/int = 1 invsclk = 0 cs sdclk 4 d2 d1 19 20 mode[1:0] = 3 rd = 0 16 d17 d16 d15 x17 x16 21 x0 x2 x1 x17 x16 x15 y17 y16 t 31 t 31 x* t 32 t 16 t 33 t 34 t 37 t 35 t 36 *a discontinuous sdclk is recommended. 0 6588-044 figure 44. slave serial data timing for reading (read after convert) sdout d0 123 busy ext/int = 1 invsclk = 0 cs sdclk 17 d1 mode[1:0] = 3 rd = 0 18 d17 d16 t 31 t 31 t 32 t 16 t 37 t 35 t 36 cnvst x* x* x* x* x* x* t 27 *a discontinuous sdclk is recommended. data = sdin 06588-045 figure 45. slave serial data timing for reading (read previous conversion during convert)
ad7631 rev. a | page 29 of 32 hardware configuration the ad7631 can be configured at any time with the dedicated hardware pins bipolar, ten, d0/ob/ 2c , and pd for parallel mode (mode[1:0] = 0, 1, or 2) or serial hardware mode (mode[1:0] = 3, hw/ sw = high). programming the ad7631 for mode selection and input range configuration can be done before or during conversion. like the reset input, the adc requires at least one acquisition time to settle, as indicated in . see for pin descriptions. note that these inputs are high impedance when using the software configuration mode. figure 46 table 6 software configuration the pins multiplexed on d[17:14] used for software configuration are: hw/ sw , scin, scclk, and sccs . the ad7631 is programmed using the dedicated write-only serial configurable port (scp) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. see for details of each bit in the configuration register. the scp can only be used in serial software mode selected with mode[1:0] = 3 and hw/ table 11 sw = low because the port is multiplexed on the parallel interface. the scp is accessed by asserting the ports chip select, sccs , and then writing scin synchronized with scclk, which (like sdclk) is edge sensitive depending on the state of invsclk. see for timing details. scin is clocked into the configuration register msb first. the configuration register is an internal shift register that begins with bit 8, the start bit. the 9 th scclk edge updates the register and allows the new settings to be used. as indicated in the timing diagram, at least one acquisition time is required from the 9 th scclk edge. bits [1:0] are reserved bits and are not written to while the scp is being updated. figure 47 the scp can be written to at any time, up to 40 mhz, and it is recommended to write to while the ad7631 is not busy converting, as detailed in figure 47 . in this mode, the full 670 ksps is not attainable because the time required for scp access is (t 31 + 9 1/scclk + t 8 ) minimum. if the full throughput is required, the scp can be written to during conversion; however, it is not recommended to write to the scp during the last 600 ns of conversion (busy = high) or performance degradation can result. in addition, the scp can be accessed in both serial master and serial slave read during and read after convert modes. note that at power-up, the configuration register is undefined. the reset input clears the configuration register (sets all bits to 0), therefore placing the configuration to 0 v to 5 v input, normal mode, and twos complemented output. table 11. configuration register description bit mnemonic description 8 start start bit. with the scp enabled ( sccs = low), when start is high, the first rising edge of scclk (invsclk = low) begins to load the register with the new configuration. 7 bipolar input range select. used in conjunction with bit 6, ten, per the following. input range (v) bipolar ten 0 to 5 low low 0 to 10 low high 5 high low 10 high high 6 ten input range select. see bit 7, bipolar. 5 pd power down. pd = low, normal operation. pd = high, power down the adc. the scp is accessible while in power down. to power up the adc, write pd = low on the next configuration setting. 4 rsv reserved. 3 rsv reserved. 2 ob/ 2c output coding. ob/ 2c = low, use twos complement output. ob/ 2c = high, use straight binary output. 1 rsv reserved. 0 rsv reserved. d0/ob/2c, pd busy hw/sw = 1 cnvst bipolar, ten t 8 pd = 0 t 8 0 6588-046 figure 46. hardware configuration timing
ad7631 rev. a | page 30 of 32 scin sccl k x start ten 123 67 busy hw/sw = 0 invsclk = 0 cnvst sccs t 8 t 36 t 35 t 37 4 pd 5 bipolar x ob/2c x 89 mode[1:0] = 3 bipolar = 0 or 1 ten = 0 or 1 pd = 0 t 33 t 34 t 31 x t 31 06588-047 figure 47. serial configuration port timing microprocessor interfacing the ad7631 is ideally suited for traditional dc measurement applications supporting a microprocessor and ac signal processing applications interfacing to a digital signal processor. the ad7631 is designed to interface with a parallel 8-bit or 18-bit wide interface, or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7631 to prevent digital noise from coupling into the adc. spi interface the ad7631 is compatible with spi and qspi digital hosts and dsps, such as blackfin? adsp-b f53x and adsp-218x/adsp-219x. figure 48 shows an interface diagram between the ad7631 and the spi-equipped adsp-219x. to accommodate the slower speed of the dsp, the ad7631 acts as a slave device, and data must be read after conversion. this mode also allows the daisy-chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading process can be initiated in response to the end-of- conversion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (timod) = 0 by writing to the spi control register (spicltx). it should be noted that to meet all timing requirements, the spi clock should be limited to 17 mbps allowing it to read an adc result in less than 1 s. when a higher sampling rate is desired, use one of the parallel interface modes. busy cs sdout sdclk cnvst ad7631* pfx spixsel (pfx) misox sckx pfx or tfsx adsp-219x* *additional pins omitted for clarity. dvdd mode[1:0] ext/int rd invsclk 06588-048 figure 48. interfacing the ad7631 to spi interface
ad7631 rev. a | page 31 of 32 application information layout guidelines w hile the ad7631 has very good immunity to noise on the power supplies, exercise care with the grounding layout. to facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the ad7631 so that the analog and digital sections are separated and confined to certain areas of the board. digital and analog ground planes should be joined in only one place, preferably underneath the ad7631, or as close as possible to the ad7631. if the ad7631 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the ad7631. t o prevent coupling noise onto the die, avoid radiating noise, and reduce feedthrough: ? do not run digital lines under the device. ? do run the analog ground plane under the ad7631. ? do shield fast switching signals, such as cnvst or clocks, with digital ground to avoid radiating noise to other sections of the board and never run them near analog signal paths. ? avoid crossover of digital and analog signals. ? run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. the power supply lines to the ad7631 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the impedance of the supplies presented to the ad7631 and to reduce the magnitude of the supply spikes. decoupled ceramic capacitors, typically 100 nf, should be placed on each of the power supplies pins, avdd, dvdd, ovdd, vcc, and vee. the capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. t he dvdd supply of the ad7631 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present and no separate supply is available, it is recommended to connect the dvdd digital supply to the analog supply avdd through an rc filter, and to connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. see figure 27 for an example of this configuration. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. t he ad7631 has four different ground pins: refgnd, agnd, dgnd, and ognd. ? refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. ? agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. ? dgnd must be tied to the analog or digital ground plane depending on the configuration. ? ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. to minimize parasitic inductances, place the decoupling capacitor close to the adc and connect it with short, thick traces. evaluating performance a recommended layout for the ad7631 is outlined in the EVAL-AD7631CBZ evaluation board documentation. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3.
ad7631 rev. a | page 32 of 32 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 49. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 080108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 50. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model 1 notes temperature range package description package option ad7631bcpz ?40c to +85c 48-lead lead frame chip scale package (lfcsp_vq) cp-48-1 ad7631bcpzrl ?40c to +85c 48-lead lead fr ame chip scale package (lfcsp_vq) cp-48-1 ad7631bstz ?40c to +85c 48-lead low prof ile quad flat package (lqfp) st-48 ad7631bstzrl ?40c to +85c 48-lead low prof ile quad flat package (lqfp) st-48 EVAL-AD7631CBZ 2 evaluation board eval-control brd3 3 controller board 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3 for evaluation/demonstrat ion purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending with the cb designators. ?2007C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06588-0-3/11(a)

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